(a) Field of the Invention
The present invention relates to exposing methods in photolithography, for manufacturing microelectronic devices and a manufacturing method of a liquid crystal display using the same.
(b) Description of the Related Art
Patterns of microelectronic devices such as liquid crystal displays and semiconductor devices are generally formed by using photolithography. In photolithography, there are two techniques for projecting a mask image onto a photoresist coated on the surface of a device in order to form a pattern. The one is to perform only one exposing step for all over the surface of the device, and the other is to perform at least two exposing steps for the surface of the device. The latter technique called step-and-repeat technique divides the surface of the device into a plurality of exposure regions, projects an image onto only one exposure region and step-and-repeat across the surface.
Although the step-and-repeat technique it may give accurate patterns relative to the former technique, it may give rise to misalignment between the exposure regions. The misalignment may be resulted from the accuracy limitation of the exposure equipment, and may result in shift, rotation and distortion of the patterns, thereby causing defects such as disconnection of the wirings and differences in electrical properties between the exposure regions.
For example, storage capacitances and parasitic capacitances between data lines and pixel electrodes and between gate electrodes and drain electrodes in a liquid crystal display may be different between the exposure regions, and this may bring about the difference in the kickback voltage.
Referring to FIG. 1, the relation between the kickback voltage and the capacitances of a liquid crystal display will be described in detail.
FIG. 1 is an equivalent circuit diagram of a pixel of a liquid crystal display. A gate line GL transmitting scanning signals and a data line DL transmitting image; signals cross each other, A gate G of a switching element such as a thin film transistor (TFT) is connected to the gate line GL, a source S is connected to the data line DL. A drain D of the TFT is connected to a liquid crystal capacitor C.sub.LC and a storage capacitor: C.sub.ST. When the TFT-turns on by a gate on voltage of the scanning signal applied to the gate G, the image signal from the data line DL is then applied to the liquid crystal, capacitor C.sub.LC and the storage capacitor C.sub.ST as a voltage. When the TFT turns off, by a gate off voltage of the scanning signal, the applied voltage across the liquid crystal capacitor C.sub.LC and the storage capacitor C.sub.ST may maintain its value. However, a parasitic capacitor C.sub.GO betweeen the gate G and the drain D drops down the voltage across the liquid crystal capacitor C.sub.LC. The voltage drop is called a kickback voltage .DELTA.V and is obtained by; the expression, ##EQU1## where C.sub.LC is the capacitance of a liquid crystal capacitor CL.sub.LC C.sub.ST is the storage capacitance of a storage capacitor C.sub.ST, C.sub.Vf is the parasitic capacitance between the gate G and the drain D, and .DELTA.V.sub.g is the voltage difference between the gate on voltage and the gate off voltage.
The difference in kickback voltages between the exposure regions may cause the difference in the brightness, which may be easily detectable near the boundaries of the exposure regions by users.
U.S. Pat. No. 5,026,143 discloses a device having a wiring, the width of which becomes wider near the boundary of the adjacent two exposure regions. Although this technique may reduce the disconnection of the wiring between the exposure regions, it may not solve the problem of the difference in the electrical properties such as kickback voltages.